Static Analysis Timing (STA) Examples

 Example (1)

1-identify the Timing paths 

2- calculate the maximum frequency of each timing path 

• the input delay is 0.3 ns
• the setup time for both FlipFlops is 0.4 ns 

Solution 

For first path is input to register 

so the equation is 

                               Tclk (clock period)+Tskew−Tsetup1≥TInput+Tpd 

                               Tclk(clock period)=Tinput+Tpd+Tsetup1-Tskew

                                                       =0.3+0.2+0.4-0.1=0.8ns

                                          Frequency=1/Tclk(clock period) =1/0.8=1.25Ghz

For second path is register to register 

so the equation is 

                             

Tclk (clock period)+Tskew−Tsetup2≥Tcq1+Tpd 

                               Tclk(clock period)=Tcq1+Tpd+Tsetup2-Tskew(Tcapture-Tlaunch)

                                                =0.01+0.5+0.4-[0.4-0]=0.51ns

                                               Frequency=1/Tclk(clock period) =1/0.51=1.96Ghz

 Example (2)

calculate the slack for setup and hold ?

• clock period is 5ns

Solution 

The timing path is from register to register 

The timing path is from register to register 

for worst case you want Tskew is minimum ,tcq1 and Tpd are maximum

slack for setup =Tclk (clock period)+Tskew−Tsetup2-Tcq1-Tpd 

=5+[2+2+5-2]-4-11-[2+2+9]=-16ns

setup Violation

so the equation for Hold is 

slack for hold=Tcq1+Tpd−Tskew−THold2

for worst case you want tcq1 and Tpd are minimum ,Tskew is maximum

slack for hold=9+[1+6+1]−[3+3+9-1]−2=1ns

No hold violation

Example (3)

1-calculate the max frequency ? 

2- How much clock skew  can the circuit tolerate before circuit introduce hold time violation ?

3-Change in circuit without changing in logic to meet timing with clock frequency 3GHz  ?

setup time= 60 ps 

hold time =20 ps

tcq min  for all ff =50 ps

tcq max  for all ff =70 ps

tpd max for all nand gates =100 ps

tpd min for all nand gates =51 ps

Solution 

part (1)

The timing path is from register to register 

in previous figure you have three Nand gates so total combinational delay will equal 3tpd and no clock idealities Tskew =0

Tclk (clock period)min+Tskew−Tsetup2≥Tcq1+3Tpd 

Tclk (clock period)min≥Tcq1+3Tpd +Tsetup5

for minimum clock period (tclk) ,take tcq1 and Tpd are maximum

                                        Tclk (clock period)min=Tcq1+3Tpd +Tsetup5

                                                                           =70+3*100+60=430ps

                                           Max frequency =1/430ps

part (2)

in previous figure you have three Nand gates so total combinational delay will equal 3tpd and I want the hold time meet timing on slack =0 ,so here I add clock idealities TSkew 

For hold time equation 

$$Tcq1+Tpd\ge THol\mathrm{d5\; +Tskew }$$

$$\mathrm{slack\; =}$$Tcq1+Tpd-THold5 -Tskew

$$$$

for max Tskew ,take tcq1 and Tpd are minimum

0 =50+3*51-20 -Tskew

Tskew =183 ps 

part (3)

For previous figure the minimum clock period is 430 ps and the max frequency is 2.3 GHz we need to increase to 3 GHz so add a flip flop to decrease the total combinational delay from 3Tpd to 2Tpd as shown figure.

The Timing path from blue register to yellow register .

                         Tclk (clock period)min=Tcq1+2Tpd +Tsetup6

                                                        =70+2*100+60=330ps

                                           Max frequency =1/330ps =3GHz.

Example (4)

1-If a design initially meets both setup and hold timing requirements, what impact would adding an inverter to the capture path have on these timing constraints?

Design before adding inverter

Design After adding inverter

For Setup :Adding an inverter introduces additional delay in the capture path.so it increases the positive clock skew ,it helps the setup time requirements.

Read also this post : Static Timing analysis Reg to Reg

For Hold :However, increasing positive skew may risk hold timing violations. Since hold time is a minimum delay requirement, any increase in the delay (due to skew) between the launch and capture clock can reduce the time margin for data to remain stable after the clock edge. Therefore, the additional delay could create a hold time issue.