Generating Output Reports and Saving Designs in Synopsys Design Compiler A Step-by-Step Tutorial - part 4

In this section, we'll cover how to generate various output reports from Synopsys Design Compiler and the process of saving your design after synthesis. This includes critical steps to ensure that the output netlist and associated files are correct and ready for subsequent design stages.

OUTPUT  REPORTS FROM DESIGN COMPILER 

Output Reports 

1- Report Design 

report_design 

2- Report Area

report_area

3- Report Latches

report_register -level_sensitive

4-Report  Flops                                                                                                                              

report_register -level_sensitive

 report_register -edge 

5-Report Constraint violators

 report_constraint  -all_violators 

6-Report Power

 report_power

7-Report QOR

report_qor

8-Report Cell

report_cell

9-Report Resources

report_resources

10- Report Timing 

 report_timing 

SAVING THE DESIGN FROM DESIGN COMPILER

Save Design

After we met the requirements, we need to write the output netlist from DC , so we need to apply some rule to make sure that the  netlist is correct.

 you have two options for output netlist 

First: source the PDK rule file ( PKD_naming_rule.script) if you have it .

secound write these rules in DC

Examples

1- make DC not use the assign statement in its output netlist

set verilogout_no_tri true

2- assume this means DC will ignore the case of the letters in net and module names

set verilogout_ignore_case true

3- unconnected nets will be marked by adding a prefix to its name

set verilogout_unconnected_prefix "UNCONNECTED"

4- show unconnected pins when creating module ports

set verilogout_show_unconnected_pins true

5- make sure that vectored ports don't get split up into single bits

set verilogout_single_bit false

6- generate a netlist without creating an EDIF schematic (altium schematic)

set edifout_netlist_only true

7-covert assign to buffer for lvs check

set_fix_multiple_port_nets -all -buffer_constants [get_designs *]

Output files 

1- ddc is database DC format, it's a library that the DC compiler can understand 

set filename [format "%s%s"  $my_toplevel ".ddc"]

write -format ddc -hierarchy -output $my_toplevel

2-save delay and parasitic data SDF for standard Delay format ,it gives you the annotated timing for each path

set filename [format "%s%s"  $my_toplevel ".sdf"]

write_sdf -version 1.0 $filename

3- save the  synthesized verilog ( Gate_level  netlist)

set filename [format "%s%s" $my_toplevel ".syn.v"]

write -format verilog -hierarchy -output $filename

4- this file is output constraint  necessary for P&R 

set filename [format "%s%s"  $my_toplevel ".sdc"]

write_sdc $filename

5- this file is output setting necessary for P&R 

write_icc2_files -environment_only -o $my_toplevel.settings.tcl