PVT Variations in VLSI: How Supply Voltage, Process, and Temperature Affect Timing

 After we discussed what's the PVT (prosses voltage Temperature variations) and how it affects timing delay .

• supply variations 

supply voltage for a chip is very less. Lets say chip operating at 1 V. so there are chances that at certain instance of time this voltage may vary . it can go to 1.1V or 0.9V. There are 2 main reasons for supply voltage variations :

1.  supply noise caused by parasitic inductance in combination with resistance and capacitance .The  current through parasitic inductance causes the voltage bounce .
2. supply voltage that any chip works on is given externally . it can come from DC source or some voltage regulator : voltage regulator will not give some voltage over a period of time . it can go  above or below the expected voltage and hence it will cause current to change making the circuit slower or faster than earlier.

 so it affects timing in design  according to Graph:

supply voltage variation 

 

• process variations 

Process variation is the deviation in attributes of Transistor during the fabrication. 

During manufacturing a die , the area at the center and that at the boundary will have different process variation 

This happens because layers which will be getting fabricated can not be uniform all over the die.

Process variation deals with physical properties of  MOSFET . so, current flowing through the channel directly

depends upon mobility ,oxide capacitance Cox , thickness Tox and ratio of width to length (W/L).

Any these parameters change ,it will result in changing the current , In other words , it will affect the delay of the circuit.

Delay decreases with increase in current .

-Delay is more for slow process MOSFETS and it is less for fast process MOSFETS.

Process variation Graph

• Temperature variations 

The temperature variation is with respect to junction and not ambient temperature .

The temperature at the junction inside the chip can vary within a big range and that's why 

temperature variation need to be considered.

Delay of a cell increases with increase in temperature. But this is not true for all technology nodes.

Foe deep sub-micron technologies this behavior is contrary .This phenomenon is called as temperature inversion.

Temperature Inversion: for technology nodes below 65nm, the delay will increase with decrease in temperature and it will be maximum at -40c . This phenomena is known as "temperature inversion"

Temperature Variation

• RC variations

RC variations is also considered as corners for the Timing delay checks. RC variation can happen because of 

fabrication process and the width of metal layer can vary from the desired one.

Usually , we have five main parasitic corners:

1. Cbest -Minimum capacitance ,Minimum delay (hold check).
2. Cwortt -Maximum capacitance, Maximum delay (setup check). 
3. RCbest - Minimum RC product (long interconnects).
4. RCworst -Maximum RC product  (long interconnects).
5. Typical -Nominal values of RC.

you have to check the number of corners that you have in PDK in each release note pdf (.rln) for PVT corners table and operating conditions  for each corner.

you choose which corner you will go on in your design , For Timing optimization you run scenarios for best _worst case , For leakage power optimization run you design on different threshold voltage (Vth)  , you must have in your PDK files for standard Vth , low Vth and high Vth.