Static and Dynamic Timing Analysis in ASIC Design: Key Timing Parameters and Constraint Violations

IN this topic ,we define the Static Timing analysis (STA) ,STA is essential stage in ASIC Folw ,going throw Timing Parmenter, timing violation in synchronous circuit in VlSI design  such as setup and hold time .we have two methods to analysis Timing Static Timing analysis (STA) and dynamic Timing analysis (DTA). 

What's the Static Timing analysis (STA)?

Static Timing analysis (STA)  is a method for determine if  each timing path meets timing requirement (timing constraint ).it is used to determine Timing violations such as setup and hold without applying input vectors. the STA tool calculate the slack of each timing path and able to find the critical path .

What's the Dynamic Timing Analysis (DTA)?

Dynamic Timing Analysis (DTA) relies on simulation like Testbench using input vectors. It provides more accurate results since it considers the actual signal waveforms.

The Key difference between Static Timing analysis and Dynamic Timing analysis 

Feature	Static Timing analysis	Dynamic Timing analysis
pros	1. much faster than Dynamic simulation 2. Exhaustive check every constrained timing path 3. no vector generation	1. accurate , can catch issues like glitches
cons	1. can't analysis asynchronous system 2. can't analyze combinational feedback loops 3. must define all constraint and boundaries	1. simulation depend on input vectors 2. takes alot of time

Timing parameters

T clk toQ (tcq)

• tcq is the time from the clock edge until the data appears at the output.
• The tcq for rising and falling outputs is different.

Tclk to Q

T propagation Delay /T combinational   Delay (Tpd)

• Propagation Delay (Tpd) is the time of standard cell depend on Input transition and output load capacitance .

You can also check out this post: Understanding Liberty File Formats (.lib vs .db).

Setup Time (T setup )

• Setup time (T setup)is the time the data has to arrive before the clock to ensure correct sampling.

Setup Timing

As shown in previous figure that we have a setup  violation when input  data changed from logic (0 )to logic (1)

during setup timing.

Hold time (T Hold)

• Hold time (T Hold) is the time the data has to be stable after the clock to ensure correct sampling.

Hold Timing

 As shown in previous figure that we have a hold violation when input data changed from logic (0 )to logic (1)

during hold timing.

Timing Paths

In STA there are three timing paths

Timing Path

1. Input to Register 

2. Register to Register 

3. Register to Output  

Each timing path has a starting point and ending point 

starting point 

1. clock pin of register.

2. Input pin.

Ending point 

1. Input data (D) of  register.

2. Output pin. 

Timing definitions 

Slack 

slack is the difference between required time and arrival time.

• slack is negative number , It means violations. 
•  slack is positive number or 0 , It means timing met.

Critical path

critical path is the timing path with minimum slack .

Required Time 

Required time specifies the time interval at which data is required to the end point .

Arrival  Time 

Arrival time specifies the time interval at which data will arrive at the end point .

Also check clock parameter part in this post   :Clock Tree Synthesis (CTS)

Timing path Definitions

Timing Constraints

•There are two main problems that can arise in synchronous logic:

•Max Delay: The data doesn’t have enough time to pass from one register to the next before the next clock edge.

•Min Delay: The data path is so short that it passes through several registers during the same clock cycle.

•Max delay violations are a result of a slow data path, including the registers' Tsetup, therefore it is often called the “Setup” path.

•Min delay violations are a result of a short data path, causing the data to change before the" Thold "has passed, therefore it is often called the “Hold” path.

Setup (max ) Timing constraint 

1.  Register to Register  (Timing Path)

starting point : input clock pin (TClk1)

Ending point : input data (D2) of Flipflop( FF2)

• without Skew and jitter (clock is ideal)

Reg to Reg timing path (ideal clock)

Setup Timing 

Explanation 

Mainly slack for setup time =capture path - launch path 

From the previous figure, it is clear that we have positive slack.

To meet the timing requirements, the following condition must hold:

$$$$Tclk (clock period)−Tsetup2≥Tcq1+Tpd

This ensures that the data has enough time to propagate through the path before the next clock edge.

The slack is calculated as:

$$\text{slack}=Tcl\mathrm{k\; (clock\; period)}-Tsetu\mathrm{p2}-Tc\mathrm{q1}-Tpd$$

Hint: Since we are considering an ideal clock, $Tclk_1 = Tclk_2$ .

• with Skew and jitter

Add clock non idealities to circuit such as Skew effect and Jitter.

Reg to Reg timing path (Nonideal clock)

Setup Timing 

Explanation

Mainly slack for setup time =capture path - launch path 

In the previous figure, I divided the analysis into two parts: one focusing on skew only, and the other including both skew and jitter for clarity.

• First Part (Skew Only): Before the green line, we see the effect of positive skew on slack. Positive skew increases the delay in the capture path, effectively adding to the clock period (Tclk).

  The condition we need to satisfy is:

  $$Tcl\mathrm{k\; (clock\; period)}+Tskew-Tsetu\mathrm{p2}\ge Tc\mathrm{q1}+Tpd$$

  The slack for this scenario is calculated as:

  $$$$slack=Tclk(clock period) +Tskew−Tsetup2−Tcq1−Tpd 

• Second Part (Skew and Jitter): At the start of the red rectangle, jitter is introduced. For jitter, we consider the worst-case scenario where it further affects the timing.

  For the launch path, jitter adds to the total delay:

  $$Tlaunch=Tc\mathrm{q1}+Tpd+Tsetu\mathrm{p2}+Tjitter$$

  For the capture path, jitter subtracts from the available time:

  $$Tcapture = Tclk + Tskew - Tjitter$$

  The condition for jitter becomes:

  $$Tclk(clock\; period)+Tskew-Tsetu\mathrm{p2}-Tjitter\ge Tc\mathrm{q1}+Tpd+Tjitter$$

  The slack in this case is:

  $$\text{slack} = Tclk + Tskew - Tsetup - Tcq - Tpd - 2Tjitter$$
  

Hold (min ) Timing constraint 

1.  Register to Register  (Timing Path)

starting point : input clock pin (TClk1)

Ending point : input data (D2) of Flipflop( FF2)

• without Skew and jitter (clock is ideal)

Hold Timing 

Explanation 

Mainly slack forhold time = launch path - capture path 

In the previous figure, we need to calculate the hold slack. There are three different scenarios:

• Case 1 and Case 2: The data remains stable after the clock edge for a duration of Thold, meaning the hold time requirement is met.

• Case 3 (marked by the red circle): The data becomes unstable because the sum of Tcq1 + Tpd is less than THold. This results in a hold time violation.

The condition to avoid hold time violations is:

$$Tcq1 + Tpd > THold$$

The slack is calculated as:

$$\text{slack} = Tcq1 + Tpd - THold$$

It is important to note that hold slack calculation is independent of the clock period (Tclk).

Hint: We assume an ideal clock, so $Tclk_1 = Tclk_2$ .

• with Skew and jitter

Hold Timing 

Explanation 

n the previous figure, I split the analysis into three cases, where all cases have equal values for Tpd and Tcq1.

• Cases 1 and 2 (highlighted by yellow and red circles) represent scenarios where the hold timing is initially met. However, when we apply positive skew to the capture path, the timing constraint is no longer satisfied, resulting in negative slack.

The formula for slack in this scenario is:

$$$$slack=Tcq1+Tpd−Tskew−THold2

• Case 3 considers the effects of both skew and jitter (worst-case scenario).
  • For the launch path, we need to subtract jitter, as it reduces the available time: $$Tlaunch = Tcq1 + Tpd - Tjitter$$
    
  • For the capture path, we need to add jitter, as it increases the required time: $$Tcapture = THold + Tskew + Tjitter$$

The condition to avoid violations is:

$$$$Tcq1+Tpd≥THold2+Tskew−2TjitterTcq1 + Tpd > THold + Tskew - 2Tjitter

The slack for this case is:

$$$$slack=Tcq1+Tpd−Tskew−THold2−2Tjitter

Conclusion:

In Case 3, the slack is more negative compared to Cases 1 and 2, meaning the timing violation is worse due to the combined effect of skew and jitter.