Logic Synthesis with Synopsys Design Compiler (DC) : A Step-by-Step Tutorial - part 2

Here's how to use DC Compiler for synthesis flow.

Design compiler Flow

DESIGN SETUP FLOW in DESIGN COMPILER

2. Open DC Shell:

Open a terminal and enter the following command to open the Design Compiler shell:

dc_shell

This command offers several options, including:

• -gui: Use the general interface.

• -64: Use the 64-bit executable (optional).

• topographical_mode: Run the shell in Topographical mode.

For a full list of options and manual of any command, use the following command:

man command_name

2. Source PDK Setup:

Source the file named synopsys_dc.setup in your PDK:

source "synopsys_dc.setup"

This file sets up the default environment for Design Compiler. If you don't have this file, you can write commands instead.

• Set Search Path:

Define the path where your design files (.lib and .db) are located:

set search_path {"standardcells .db/.lib path" "iocells .db/.lib path"}

If you use macros, add the macro path to the command.

• Link Libraries:

Connect your design to all library components and design references by linking them:

set link_library {* standardcells.db macro.db iocells.db}

This command links the specified libraries to your design.

• Set Target Library:

Define the target library for mapping and optimizing your design:

set target_library {standardcells.db}

This library will be used to map your RTL code into technology-specific standard cells and optimize the design for timing, power, and area.

• Set Symbol Library (Optional):

Define the symbol library used for generating the design schematic:

set symbol_library={symbol library.slid}

This step is optional, but it's useful for visualizing your design.

Note: This is a simplified overview of the Design Compiler flow. Additional steps may be required depending on your specific design and optimization goals.

GUI Flow For Design setup 

dc_shell -gui

1. From the File menu, select Setup

2. put each path for libraries 

For Best Practice 

if you don't have symbol library delete it from setup

 Steps to Read HDL (Verilog /VHDL) Code in Synopsys Design Compiler

Reading RTL in DC

READING HDLS IN SYNOPSYS DESIGN COMPILER

First, you need to create a directory named "WORK" where DC will place intermediate files. Before that, it's good practice to remove any files from previous runs.

• remove all files from previous runs  

sh rm -rf WORK

• create new directory mkdir name " work "

sh mkdir -p WORK

• define path of  "WORK"

define_design_lib WORK -path ./WORK

Second perform analyze command to read HDL code , check error in you RTL code , create from your RTL an intermediate files(.mr and .st) in work directory

analyze -format verilog -lib WORK {verilog_files}

• - format  option changes depend on your HDL language  if you are using system verilog ,soyour format is  sverilog.
• -lib option your directory which locate the intermediate files. 

you can write multiple analyze for each RTL file if it 's written in mixed format.

Third perform elaborate command to translate the intermediate design files into a technology-independent GTECH cells generic technology inside DC compiler.

GTECH cells 

set my_toplevel toplevel_of_design_name

elaborate $my_toplevel -architecture verilog -library WORK

• -architecture option changes depend on your HDL language .
•  -library option your directory which locate the intermediate files.

you can use read command to perform the same operations as the analyze and the elaborate commands in a single step , however I prefer analyze & elaborate for beginners cause  it clarify the errors and unsynthizable statements  inside your RTL .

read -format verilog verilog_files.v

After reading your HDL , for a good practice use these commands 

👉link command  to check if all libraries are loaded into your design .

👉current-design command to know which HDL top you are working on .

👉check design command   checks your current design for connectivity and hierarchy issues, for example:  Missing ports or unconnected input pins , multiple instantiations .

link

current_design $my_toplevel

check_design

GUI Flow For Reading HDLS

 

1- choose file from dc gui

2-From file choose analyze

add your HDL files ,analyze command  creates the work library automatically

2- From the File menu, select Elaborate.

    

   Choose the WORK library and run the elaborate command on the top-level design file.

3- Use the Link Design  command from the GUI.

4-From the Design menu, select CheckDesign.

For Best Practice 

If you have error " unresolved references. For more detailed information, use the "link" command. (UID-341)"