Clock Tree Synthesis (CTS)

Understanding Clock Tree Synthesis (CTS) in VLSI Design

Clock Tree Synthesis (CTS) is important in VLSI design, ensuring efficient clock signal distribution across digital circuits. This process minimizes clock skew and optimizes insertion delay, which is essential for reliable chip operation.

What is Clock Tree Synthesis (CTS)?

clock tree synthesis  (CTS) is building a buffer/inverter network to balance the related sequential elements (such as flip-flops and registers) s belong to same clock domain targeting global skew of each clock domain ~0. Essentially, CTS ensures that the clock signal reaches various parts of the chip simultaneously, maintaining synchronization across the circuit.

After placement, where the location of each standard cell is determined, we have already optimized timing, area, and minimized congestion. Up to this point, we have an ideal clock. Now, we need to create a balance between the clock signals during Clock Tree Synthesis (CTS).

Types of Clock Tree Structure

• Geometric structures

1- H_ structure

The most commonly used structure in Clock Tree Synthesis (CTS) is the H-Tree structure. The H-Tree is favored because it provides a symmetric and balanced clock distribution network, which helps minimize clock skew

    H-structure

2- X_ structure

The X-Tree similar to the H-Tree structure, the X-Tree is designed to provide a balanced and symmetric clock distribution network. However, it differs in its geometric configuration.

        X-structure

3-Pi-structure

 

The Pi-structure is designed to provide a balanced clock distribution while also focusing on specific design requirements, such as minimizing skew and handling complex layouts.

        Pi_structure

• Electrical structures

1-RC approach

The RC structure in Clock Tree Synthesis (CTS) refers to a clock distribution network that models the resistance (R) and capacitance (C) of the interconnects. Unlike geometric structures, the RC structure focuses on optimizing the electrical properties of the clock network to achieve minimal skew and delay.

                RC_structure 

cClock Parameters in Clock Tree synthesis (CTS)

1. clock skew 

Clock skew is the difference in clock arrival time at two different registers, Skew can be positive or negative.

   

        Clock skew

Clock skew is calculated as the difference between the capture clock and the launch clock. Referring to the previous figure, the skew can be calculated as follows:

$\text{Skew} = \text{Capture Clock} - \text{Launch Clock} = 5\text{ ns} - 3\text{ ns} = 2\text{ ns}$"

Positive Skew 

IF the capture clock comes late than launch clock then it is called +ve skew.

     Positive Skew

Negative Skew 

IF the capture clock comes early than launch clock then it is called -ve skew.

Negative Skew

Types of Clock Skew

1.Local Skew

Local skew is the Difference in  arrival time clock between two related flipflop.

2.Global Skew or (Target Skew)

Global skew is the Difference in  arrival time of clock signal at clock pin of non-related flipflop. Clock Tree Synthesis aims to minimize global skew (~0).

Local Skew VS Global Skew

Global skew, also known as the difference between the shortest clock path delay and the longest clock path delay between two flip-flops, can be calculated as follows:

Referring to the previous figure:

$\text{" Global Skew}=\text{Longest Path}-\text{Shortest Path}=(10\text{ ns}+3\text{ ns})-3\text{ ns}=10\text{ ns }$"

2. Clock Latency  

 The total delay from the clock source (e.g., PLL) to the clock pin of a register. It includes:

• Source Latency: Delay from the clock's original point (PLL) to its definition point of clock in the design.
• Network Latency (Insertion Delay): Delay from the clock definition point to the clock pin of the register.

Source -Network Latency Delay

 

3. Jitter 

Jitter is the variations in clock period between different clock cycles , due to inconsistencies in the PLL's output , It generates clock cycle in different width.

Jitter 

 

4. slew  

Slew is the rate of change of the clock signal transition (Trise/Tfall), which can affect the performance of the clock distribution network.

              Slew

Why is Clock Tree Synthesis (CTS) necessary in the ASIC flow?

In ASIC design, we can't simply route the clock nets to all flip-flops in the same clock domain without proper optimization. CTS is essential because it ensures that the clock network is optimized for timing, area, and power. 

Clock Tree

Start of Clock tree synthesis (CTS)

Do checks

• Placement -done.
• Power and ground nets -prerouted.
• Estimated congestion-acceptable.
• Estimated Timing -acceptable.
• No violation in constraints max cap/transitions.
• High fanout synthesized nets (such as scan nets ,Reset ).

What is The Clock tree synthesis (CTS)goals?

1. Minimizing Clock Skew .

2. Minimize the insertion delay .

3. Meet the clock tree logical design constraints rule (Max fanout, Max load capacitance, Max transition delay, Max buffer length).

The CTS Process

1. Clock Tree Specification: The process begins with defining the clock tree specifications, including the clock sources, the locations of clock sinks (such as flip-flops).

• Defining the Starting , Ending and Exceptions point of clock tree

Starting Point 

clock source

• An input clock port 

Clock Source -Input port

• An output pin from gated cell (AND gate , OR gate ,MUX )

Clock Source -GATED CELL

CLOCK SINKS

clock sinks is that pins that receive the clock signal

• Stop pins (input pins of clock in Flip-Flops , Latches )

Clock sink-stop pin

• Float pin /insertion delay 

IF you have macro /IP block and it has insertion delay we need to define float pin delay for balancing skew.

clock sinks-Float pin

• Exclude pin 

Exclude pins /Ignore pins  are that pins on the clock net that will not be considered a sink in any skew balancing.

clock sink-Ignore pin

2. Clock Net Routing : Clock nets route using Non-default routing rules this is rules are used to make clock routes less sensitive to cross talk. 

Using higher and thicker metals: Reduces resistance and make capacitance less to the substrate.

Shielding: Placing the clock net between power and ground signals to reduce noise.

Non-default Routing Rules: Using double width and double spacing for clock nets.

Default Routing Rule Vs Non-Default Routing Rule

   

    Shielding

3. Clock Tree Optimization and Skew Optimization: Optimize clock by inserting and sizing buffers within the clock network to balance the clock tree.

Clock Tree Optimization Techniques 

1- Gate and Buffer Sizing

Gate - Buffer Sizing

2- Gate and Buffer relocation

Gate - Buffer Relocation

 3- Insertion Delay 

Insertion Delay

4. Validation and Analysis: The final step involves rigorous validation and analysis of the clock tree to ensure that it meets the design specifications. This includes timing analysis, skew analysis, and power analysis.