Design For Test (DFT)

The importance of Design for test (DFT) in ASIC Flow to measure the manufacture defects even if the chip was well designed and functionally correct. It simulated and synthesized just fine.

What 's The Manufacture Defects ?

Physical defects 

• Silicon Defects: Flaws in the silicon substrate during the manufacturing process. 
• Photolithography Defects: Issues during the process of transferring patterns onto silicon wafers. 
• Mask Contamination: Imperfections on masks used for patterning wafers.  
• Process Variations: Variation in fabrication leading to inconsistent chip performance.
• Defective Oxide: Issues in the oxide layer.

Electrical Effects 

• Shorts (Bridging Faults) : Cause wider wires in power mesh .
• Opens : Cause smaller wire in power mesh . 
• Transistor Stuck On/Open : Transistors stuck in an “on” or “off” state due to manufacturing defects. 
• Changes in Threshold Voltage.

Logical Effects

• Logic Stuck-at-0/1: An internal node stuck at 0 or 1 whatever the primary input. 
• Slower Transitions (Delay Fault) : long transitions.
• AND-bridging, OR-bridging : Two logical gates behave incorrectly. 

Why Test for Manufacturing Defects?

• To detect manufacturing defects and reject those parts before shipment .
• To debug the manufacturing process. 
• To improve process yield .

How  Test  Manufacture Performance ?

The Manufacture performance in VLSI Design measure by using the Automatic Test Equipment (ATE) applies input stimulus to the Device Under Test (DUT) and measures the output response. If the ATE observes a response different from the expected response, the DUT fails the manufacturing test. 

The Stuck-At Fault Model 

Stuck-At Fault (SAF): A logical model representing the effects of an underlying physical defect.

Stuck-At Fault (SAF)

Stuck-At Fault (SAF) assumes that a node is either permanently stuck at a logical 0 (SA0) or at a logical 1 (SA1).This model allows engineers to focus on observable symptoms rather than the exact physical causes of defects. 

The SAF shows that an Inverter Gate model the physical defects causes and electrical short on the input, stuck the input at logic 0 (SA0) which can be observed as a logical 1 (SA1) on the output.

Algorithm for Detecting Stuck-At Fault  (SAF)

SAF algorithm

The D Algorithm is a classic approach for detecting SAFs in combinational logic. It generates test patterns for each fault one at a time (either SA0 or SA1). This algorithm is fundamental in Automatic Test Pattern Generation (ATPG) tools.

• If this SA0 fault is present then the Y node stays at logic 0
• If not present, then  the Y node is driven to its normal value

Controllability 

Is the ability to set internal nodes to a specific value.

 Controllability 

Pick a specific fault (e.g., SA0 on U1 output).

Generate a detectable error (fault effect) at the input ports.

Measure the difference between fault-free and faulty behavior.

Observability 

Is the ability to propagate the fault effect from an internal node to a primary output port.

  

observability

Ensure the fault effect can be observed at the output.

Measure the primary output to detect any fault.

Fault Coverage

High fault coverage directly correlates with detecting more manufacturing defects. Testing aims to achieve as high a fault coverage as possible, ensuring the majority of internal nodes are checked.

Fault coverage = Number of detectable faults/Total number of possible faults.

Number of Detectable Faults: The number of faults that can be identified during the testing process. These are the faults for which the test patterns have been generated.

Total Number of Possible Faults: The total number of potential faults in the design, based on the fault model being used (stuck-at faults, transition faults, etc.).

Testing a Multistage, Pipelined Design 

Testing complex designs like multistage pipelines can be challenging. Each fault requires controlling inputs and observing results downstream. One common solution is Scan Chain Insertion, where all flip-flops are replaced with scannable versions, and connected serially (stitched). This allows for easy data shifting in and out, improving controllability and observability.

Non-San Register Vs Scan Register

Violations due to Scan Register Replacement 

Scan replacement introduces timing violations due to additional registers in the scan chain. 

  1. Scan chain  violation 

Issue : Scan register larger than Non-scan register less combination time violate hold  time.

or additional fanout more capacitive load due to scan register chain violate setup time.

Impact :This can lead to incorrect data during the shifting of test patterns and erroneous fault detection.

solution :Perform timing-aware synthesis and timing analysis specifically for scan chains.

  2. Excessive Power Consumption

Issue: Scan-shift operations involve toggling a large number of flip-flops simultaneously, which can lead to excessive dynamic power consumption during testing.

Impact: This can cause IR drop issues, excessive heat generation, or even damage the chip under test (CUT).

solution:

• Employ power-aware scan techniques, such as partitioning scan chains into smaller segments and enabling staggered shifting.

• Use clock gating techniques during scan shifting to reduce switching activity.