Continuing with the explanation of Synopsys Design Constraints (SDC), let's delve deeper into how SDCs help in meeting area, timing requirements while accommodating synchronous and asynchronous multiple clock designs performance requirements in ASIC (Application specific Integrated Circuit) design.
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The SDC file is a crucial aspect of the design process, defining constraints that guide synthesis, placement, routing, and timing analysis tools to produce an optimized design in VLSI that meets the project’s specifications.
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| SYNTHESIS FLOW |
AREA Constraints in SDC Files
Definition and Determination of Area Constraints
The area unit is typically defined by the library supplier in the Liberty file (.lib). Common units include:
- 2-input NAND gates
- Transistors
- Area in square micrometers (µm²), square millimeters (mm²), etc.
If the area unit is not specified in the library, you should contact the library supplier to confirm. The value for set_max_area is usually determined by:
- Project specifications or guidance from the project lead.
- If migrating to a newer technology, using a smaller percentage of the previous design's area.
- Estimations based on prior experience.
Using set_max_area
# Set the maximum area constraint
set_max_area <value>
Setting set_max_area 0 is acceptable ?
yes ,it's acceptable when the goal is to prioritize area optimization over timing . In this case, the synthesis tool will perform the best optimization for minimal area.
Synchronous Multiple Clock Designs
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| Synchronous multiple clock design |
as shown in previous figure that the main clock is 3 GHz and the other clocks deveided from main clock
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| Input Delay Value |
Creating Clocks
First, define the clock periods for all clocks involved.
create_clock -period 3.0 -name CLKA
create_clock -period 2.0 [get_ports CLKC]
# Input delay on CLKA
set_input_delay 0.55 -clock CLKA -max [get_ports IN1]
Multiple Clock Output Delay
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| Output Delay Value |
Creating Clocks
First, define the clock periods for all clocks involved.
# Define clocks
create_clock -period [expr 1000/750.0] -name CLKD
create_clock -period 1.0 -name CLKE
create_clock -period 2.0 [get_ports CLKC]
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| clock divider |
Similarly, constrain the output delay for signals associated with each clock.
# Output delay on CLKD and CLKE
set_output_delay -max 0.15 -clock CLKD [get_ports OUT1]
set_output_delay -max 0.52 -clock CLKE -add_delay [get_ports OUT1]
Asynchronous Multiple Clock Designs
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| Asynchronous Multiple Clock Designs |
For asynchronous multiple clock designs, you need to specify false paths to prevent timing-based synthesis and analysis across asynchronous clock boundaries. This will prevent DC from wasting time trying to get the asynchronous path to “meet timing". You can't use create_clock command in DESIGN COMPILER (DC) to define as Asynchronous Clock this is only for synchronous Clocks .
Defining False Paths
EXAMPLES
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| Two Multiplexers Example |
Consider a scenario with two multiplexers, MUX1 and MUX2, each having two inputs (IN0, IN1) and a common output. In this setup:
- MUX1/IN0 to MUX2/IN1: If
IN0ofMUX1is selected, it is impossible for this data to propagate throughIN1ofMUX2. - MUX1/IN1 to MUX2/IN0: Similarly, if
IN1ofMUX1is selected, data cannot propagate throughIN0ofMUX2.
Since these paths are logically impossible, they are considered false paths.
# False paths between multiplexers
set_false_path -through [get_pins MUX1/IN0] -through [get_pins MUX2/IN1]
set_false_path -through [get_pins MUX1/IN1] -through [get_pins MUX2/IN0]
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| Two clocks Example |
CLKA and CLKB. These clocks are asynchronous to each other, meaning there is no fixed phase relationship between them. Paths that cross from one clock domain to the other might not require timing optimization, as the timing constraints would not apply across these domains.Example 2: False Paths Between Clocks
# False paths between CLKA and CLKB
set_false_path -from [get_clocks CLKA] -to [get_clocks CLKB]
set_false_path -from [get_clocks CLKB] -to [get_clocks CLKA]
For designs with multiple clocks where you want to declare all paths between specific clock groups as false, the set_clock_groups command is more efficient.
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| Multiple clock Design |
Example Using set_clock_groups:
# Define clock groups as asynchronous
set_clock_groups -asynchronous \
-group {CLKA} \
-group {CLKB} \
-group {CLKC} \
-group {CLKD}
Multi-Cycle Paths
By default, paths are timed for a single cycle, but multi-cycle paths allow additional cycles for data to be captured.
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| Multi-Cycle path |
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| default clock cycle |
However, sometimes a designer might need to provide some additional cycles before the data is to be captured. The paths which get additional cycles are called multi cycle paths
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| Synchronous Multiple cycle path of two |
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| Multiple cycle path Example |
Example: Multi-Cycle Path of Two Cycles
# Define a multi-cycle path with setup and hold
set_multicycle_path -setup 2 -from A_reg/clocked_on -through U_Mult/Out -to B_reg/next_state
set_multicycle_path -hold 1 -from A_reg/clocked_on -through U_Mult/Out -to B_reg/next_state
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