Efficient Design Compiler Flow For Optimization in Synthesis : A Step-by-Step Tutorial - part 3

Design Optimization in Synthesis

Design optimization is a critical step in the synthesis process where the Design Compiler attempts to implement a combination of library cells that meet the functional, speed, and area requirements of your design. The optimization process transforms the design into a technology-specific target library, focusing on standard cells based on constraints or attributes.

Design compiler Flow 

DC flow

Design compiler perform optimization on levels

Optimization levels 

What Is Architectural optimization Level ? 

 Architectural optimization works on the HDL description , including high level synthesis tasks .

High-Level Synthesis

1. Resource Sharing
2. Implementation Selection
3. Reordering Operators
4. Sharing Common Subexpressions

These high-level synthesis decisions are made during compile. Before compile, while RTL is being read in (during the elaboration phase) some additional architectural manipulation takes place, including identifying sharable or merge-able operators. 

Resource Sharing

Resource Sharing

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Implementation Selection

Multiple implementations for singleton arithmetic operators, available in the Standard Library, allow DC to evaluate speed/area tradeoffs and choose the best - the smallest that meets timing

Implementation Selection

Once selected, each implementation is then optimized for the target technology library 

 The ‘High Performance’ DesignWare Library allows more choices – discussed later

There is also a DesignWare library available, which gives DC many more high-performance implementation possibilities arithmetic operators (including a datapath generator for adders, subtractors and multiplier), as well as an immense collection of standard soft IP blocks that can be instantiated in designs and optimized for the target technology. Access to the DesignWare library requires a DesignWare license, as well as a couple of variables settings. Discussed further in a later Unit

Operator Reordering

Operators are re-ordered to reduce critical path delays

Operator Reordering

What Is Logic-Level Optimization? 

After high-level synthesis, circuit function is still represented by GTECH parts 

•   One optimization process occurs by default during logic-level optimization Structuring

 Structuring:

• Reduces logic using common sub-expressions
• speed acceleration  as well as area optimization
• constraint-driven

Structuring

Structuring is a logic optimization step that adds intermediate variables and logic structure to a design. During structuring, Design Compiler searches for sub-functions that can be factored out.

What Is Gate-Level Optimization?

Gate_level optimiztion based on Combinational and Sequential Mapping , DRC fixing.

• Combinational Mapping and Optimization

The process of selecting the best combinational logic gates from the target library to generate a design that meets timing and area goals.

Combinational Mapping

•  Sequential Mapping and Optimization

The process by which DC maps to sequential cells from the technology library:  Tries to save speed and area by using more complex sequential cells (optimization)

Sequential Mapping

Mapping optimization by default tries to meet the following constraints:

•   Design rule constraints (DRCs) 
•   Timing constraints 
• Area constraint 
•  From Highest priority To Lowest priority 

DRCs: 

• Technology libraries contain vendor-specific design rules for each cell, e.g. max_capacitance/transition 
• DRC fixing entails inserting/removing buffers and re-sizing gates that has higher priority than delay, by default.

Optimization Flow in DC Design Compiler :

First: source constraint file 

source ./constrains.tcl

link

Second : use compile command ,it's mega command to apply the tree optimization levels

To flatten the hierarchy to allow optimization to cross hierarchy boundaries 

  ungroup -flatten -all

compile -map_effort medium

• -map_effort option to make the tool apply effort for optimization area,timing and power 

For optimization in area over time 

compile_ultra -no_autoungroup -area_high_effort_script

For optimization in time over area

compile_ultra -no_autoungroup -retime -incremental

 by default ungroup used with compile_ultra and compile 

For Best Practice 

•  report if ungroup

report_auto_ungroup

•  check internal DC representation for design consistency

check_design

•  verifies timing setup is complete

check_timing

•  report design size and object counts

report_area

•  report path group

report_path_group

•  reports design database constraints attributes

report_timing_requirements

GUI FLOW

From Design choose compile Design or Compile Ultra

GUI window