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Routing

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Mastering Routing in VLSI Design

Routing is a crucial phase in VLSI (Very Large Scale Integration) design, where physical connections are created between various components on a chip. After the placement phase determines the location of each cell, routing connects the nets, ensuring electrical signals travel efficiently between them.

Challenges of Routing in ASIC Flow

  • Geometrical Considerations: Each metal layer has a cost associated with its use, and careful choices must be made to avoid routing congestion.
  • Electrical Considerations: Timing across nets must be verified to ensure signal integrity, and crosstalk (unwanted interference between wires) must be minimized. The routing algorithm must account for horizontal and vertical connections while adhering to the fixed number of metal layers available in the design.

Routing Algorithms

Manhattan Routing

Manhattan routing relies on strict horizontal and vertical connections, avoiding diagonal paths. This method allocates one set of metal layers for horizontal routes and another for vertical ones. Each technology node has a metal layer stack. The separation of layers helps prevent wire crossings and minimizes signal interference, which improves signal integrity and reduces congestion.

Metallization 

Grid Structure

The core area of the design is divided into small squares, creating a grid structure. The grid is composed of tracks corresponding to the metal layers used for wiring. Routing within the grid follows the Manhattan-style approach.


                                                                    Grid Structure


Lee Routing

Lee Routing finds the shortest path between two pins on a grid but routes one net at a time. However, this can lead to blockages when previously routed wires occupy optimal grid points for a subsequent net, causing several problems:

  • Congestion: The grid becomes crowded with wires, leaving fewer paths for later nets.
  • Deadlock: If no available paths remain, the algorithm may fail, requiring earlier routes to be unrouted and redone.
  • Suboptimal Paths: Blockages force the use of longer paths, increasing wire length, delay, and power consumption.
Lee Routing 

Solution: Maze Routing

Maze Routing is an advanced version of Lee’s Algorithm that uses heuristics to avoid congested areas. It follows three key steps:

  1. Expansion: All possible paths are explored from the source to the target.
  2. Backtrack: The shortest path is selected by tracing back from the target.
  3. Cleanup: The final path is marked, ensuring it is avoided during the routing of subsequent nets.
Maze Routing

The Routing Flow

Routing in VLSI involves connecting components such as transistors, resistors, and capacitors on a semiconductor chip. It is divided into two main stages:

Global Routing

In global routing, the design area is divided into regions known as global routing cells (Gcells). Each net is assigned to a specific metal layer and Gcell area, but no actual interconnections are made. The goals of this stage include:

  • Avoiding Congestion: Steering clear of congested areas.
  • Minimizing Timing: Reducing detours that increase wire length.

Track Assignment

After global routing, track assignment determines which track (horizontal or vertical) each net will follow. This stage doesn't enforce Design Rule Checks (DRCs) but aims to:

  • Minimize Vias: Reducing the number of vias by using straight traces.
  • Prepare for Detailed Routing: Setting up the design for the final routing phase.

Detailed Routing

In detailed routing, the exact routes are determined for wires on specific grid lines. This stage resolves violations from the global routing and track assignment phases. Detailed routing handles:

  • Overlaps: Avoiding overlaps between wires.
  • Wire Length: Minimizing the length of interconnections.
  • Congestion: Fixing congestion issues and reducing delays.

Search and Repair 

search and Repair fixes the remaining DRC violations through multiple loops using progressively large SBox sizes, In this stage you check only the DRC violations in Technology file , you have to run the sign-off DRC in physical verification stage.

Key Challenges in VLSI Routing

  1. Minimizing Signal Delay: Delays are caused by wire length and capacitance, so minimizing these factors is critical for performance.
  2. Avoiding Crosstalk: Signals in adjacent wires may interfere with each other, leading to data corruption.
  3. Optimizing Area and Power: Efficient routing must balance minimal area usage and power consumption without compromising performance.

Best Practices for Effective Routing

  • Layer Assignment: Use different metal layers for specific directions (horizontal or vertical) to reduce congestion.
  • Wire Sizing and Spacing: Adjusting wire widths and spacing optimizes resistance and capacitance, improving signal integrity.
  • Shielding: Use shielding to protect sensitive signals from crosstalk and interference.
  • Timing Analysis: Conduct thorough timing analysis to ensure signal paths meet required constraints, with no timing violations.



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