PowerPlanning

 What's The Power Planning in ASIC?

Power Planning is to decide how the power will be delivered to the all cells on chip including the  input/output pad  cells , standard cells and macro/IP cells.

 The Big Picture 

      Inputs and Outputs of Power Planning 

 Inputs of Power Planning 

• Dynamic Power : that's came from power tools like Prim Rail from Synopsys not from synthesis tools cause synthesis tools like DC compiler from Synopsys calculate the power on default toggling rate not exact .
• Static Power : that's came from synthesis power tools calculated in power report . 
• Floor planning grid that done in previous step.

Outputs of Power Planning 

• you have to meet the target IR drop approximate (10%-22%).
• you have to meet the Electromigration (EM) mentioned in PDK documents.
• you have to meet the Total power (Dynamic and Static).
• Power grid done 

 What's The IR Voltage Drop?

IR Drop is the drop in supply voltage over the length of the supply line.

After the power grid done the resistance matrix is constructed , average current calculated of each gate , so we can determine the IR matrix  at each node

IR Drop

What's The Electromigration (EM)?

EM

Electromigration refers to the gradual displacement of the metal atoms of a conductor as a result of the current flowing through that conductor. 

When a high current density passes through a metal interconnect ,the momentum of current carrying electrons may get transferred to the metal ions during the collision between them.

Due to the momentum transfer, the metal ions may get drifted in the direction of motion of electrons . such drift of metal ions from its original position is called the electro migration effect.

Two failures due to EM

1. can cause open (single wire)
2. can cause short (bridge between two wires)

       open and shorts in wires

Even without open or short in wires can cause performance degradation.

Target of  PowerPlanning 

Power mesh grid

Target of the Power Planning to create the  power mesh  grid this is came with some definitions :

1. Core Ring : Rings around the core and  specified by two rings one for power and ground . 
2. Trunks : it's a stack of metals connected to Core ring to deliver the power and the ground from supply voltage.
3.  Straps : it's specified as a horizontal straps for both power and ground and a vertical for both  power and ground for voltage stabilization , connected to core Ring to connect  all cells in core.
4.  Standard cells Rail : each standard cell has two pins for power and ground need to be connected ,so we put rails on each site row in core area to connect the pins.
5. i/o Ring :like cells in core area i/o pads need to connected to power and ground , some cases the i/o Ring is built in  no need to create  it check the pdk documentation . 

PowerPlanning Flow in ICC2  

                                                                                 PowerPlanning Flow 

User can specify the width of core and i/o ring , number and width  of straps to meet target IR Drop and total power budget.

1-create power nets and connect them to power signals  

create_net -power VDD

create_net -ground VSS

 get_nets VDD

 change_selection [get_nets VDD]

 set_attribute -objects [get_nets VDD] -name net_type -value power

 connect_pg_net -net VDD [get_pins -physical_context *VDD]

•  report_app_option *power*

 set_app_option -name mv.pg.default_power_supply_net_name  -value VDD

 set_app_option -name mv.pg.default_power_supply_port_name -value VDD

 2-create ground nets and connect them to ground signals   

 get_nets VSS

 change_selection [get_nets VSS]

 set_attribute -objects [get_nets VSS] -name net_type -value ground

 connect_pg_net -net VSS [get_pins -physical_context *VSS]

• report_app_option *ground*

 set_app_option -name mv.pg.default_ground_supply_net_name  -value VSS

 set_app_option -name mv.pg.default_ground_supply_port_name -value VSS

3-calculate  power  budget ( initial power estimation , Average current , max current density)

3- create power ring 

create_pg_ring_pattern ring_pattern -horizontal_layer layer_metal  \

  -horizontal_width {width_size} -horizontal_spacing {spacing_size} \

   -vertical_layer  layer_metal  -vertical_width {width_size} -vertical_spacing {spacing_size}

set_pg_strategy core_ring \

   -pattern {{name: ring_pattern} \

   {nets: {VDD VSS}} {offset: {3 3}}} -core

compile_pg -strategies core_ring

Power ring 

4-straps and macro connection 

• vertical straps 

 create_pg_strap -layer M8 \

                 -direction vertical \

                 -width 3 \

                 -start 110 \

                 -stop 1690 \

                 -pitch 15 \

                 -net VSS  \

                 -extend_low outermost_ring \

                 -extend_high outermost_ring

 create_pg_strap -layer M8 \

                 -direction vertical \

                 -width 3 \

                 -start 115  \

                 -stop 1695 \

                 -pitch 15 \

                 -net VDD  \

                 -extend_low innermost_ring \

                 -extend_high innermost_ring

• horizontal straps

 create_pg_strap -layer M9 \

                 -direction horizontal \

                 -width 3 \

                 -start 110 \

                 -stop 1395 \

                 -pitch 15 \

                 -net VSS  \

                 -extend_low outermost_ring \

                 -extend_high outermost_ring

 create_pg_strap -layer M9 \

                 -direction horizontal \

                 -width 3 \

                 -start 115  \

                 -stop 1390 \

                 -pitch 15 \

                 -net VDD  \

                 -extend_low innermost_ring \

                 -extend_high innermost_ring

Power straps

 5-standard cells rails on M1

create_pg_std_cell_conn_pattern rail_pattern -layers { M1}

set_pg_strategy M1_rail -core -pattern {{name :rail_pattern}{nets : {VDD VSS}}} -blockage {{nets:VDD VSS}{macros:all}}  

compile_pg -strategies  M1_rail

power rail on metal one

6- Trunks 

 cannot create this cause tool  (try manual)

create_pg_macro_conn_pattern ring_pin_pattern \

   -pin_conn_type scattered_pin \

   -width { 1.62 1.62 } -layers {M8 M9} -nets { VDD}\

    -pitch { 0.54 0.54}

set_pg_strategy pad_to_ring -macros {vdd_l vdd_b  vdd_r vdd_t } \

    -pattern {{name:ring_pin_pattern}{nets: VDD}}

compile_pg -strategies {pad_to_ring rail_via_rule} -ignore_drc

power trunks

7-insert well_taps array 

create_tap_cells -lib_cell */TAPCELLBWP7T  -distance 25 -pattern stagger -enable_prerouted_net_check 

connect_pg_net -automatic -all_blocks -verbose

Tap array

8- synthesis  power to meet target IR and power budget

read_parasitic_tech -name {best}  -tlup {.tluplus} -layermap {star.map_9M}

read_parasitic_tech -name {worst} -tlup {.tluplus} -layermap {star.map_9M} 

set_parasitic_parameters -early_spec worst -late_spec best

analyze_power_plan -nets [get_nets -design [current_block] {VSS VDD}] -power_budget 500 -voltage 1.2

 

9- save block

save_block -as ${design}_powerplanning