Placement

PNR Flow

 What's The Placement in ASIC?

placement is to determine the location of standard cells inside the core boundary.

After the designed Floorplanning and Powerplanning ,we will move to placement of  Standardcells (Std). 

What's the Target of  Placement ?

1. provide legal location of cells.
2. Timing ,Area,Power Optimization.
3. Congestion Optimization (Minimize Congestion).

 Inputs of Placement

1. synthesized gate level netlist.
2. floorplan and power plan.
3. constraint files.

Outputs of Placement 

1. placed standard cells
2. Best timing.
3. minima congestion .

Placement Flow

 placement done in two stages 

  1. Global placement  

    Trying to minimize the number of connection between the gate cells .

Global placement

   2. Detailed (coarse) placement 

   legalize cells inside core area.

  minimize wirelength for cells

  finish placement of cells without congestion

Detailed placement

High Fanout synthesis 

High Fanout synthesis (HFS)  is the process of adding buffers and inverters to split the maximum number of fanout this is done in placement stage  , which some specific nets have high number of fanout , as mention in  that we have constraint of default maximum fanout . 

As foremention that in placement  stage we have to achieve best timing and uncongested design , so we have two algorithm Timing_Driven placement and Congestion_Driven placement.

Timing-Driven Placement Algorithm 

Timing-driven placement tries to place critical path cells close together to reduce net RCs and to meet setup timing 

• RCs are based on Virtual Route (VR)

    Layers are not taken into consideration 

Virtual Route (VR)

• Timing-driven placement based on Virtual Route 

    Tries to place cells along timing-critical paths close together to reduce net RCs and meet setup timing 

    Net RCs are based on Virtual Routing estimates

as we know that we have estimate parasitic in .lib file based on fanout called Wire Load Model (WLM)

Timing-driven placement

Congestion 

Congestion occurs when the number of required routing tracks exceeds the number of available tracks. 

• Congestion can be estimated from the results of a quick global route as shown in next figure and make what we call channel congestion each channel has Query Point which calculate demand/capacity .

Channel Congestion

          Overflow on each edge = Routing Demand - Routing Supply 0 (otherwise) 

                                       Total Overflow = overflow all edge

                                                     Overflow on each edge

As shown in previous figure the overflow on each edge for red layer that the Demand more than Capacity based on congestion , so you have to reduce congestion .

Issues with Congestion 

• If congestion is not too severe, the actual route can be detoured around the congested area. • The detoured nets will have worse RC delay compared to the VR estimates.

 • In highly congested areas, delay estimates during placement will be optimistic.

Detour

   Not routable or severely congested design

• It is important to minimize or eliminate congestion before continuing

• Severe congestion can cause a design to be un-routable.

Congestion Maps 

• Congestion maps are displayed by the backend tool to help us evaluate the total congestion, identify and fix congestion hot spots.

Congestion-driven Placement

Congestion Reduction 

• The tool tries to evaluate congestion hotspots and spread the cells (lower utilization) in the area to reduce congestion.

 • The tool can also choose cell location based on congestion, rather than wire-length.

Un-routable Layout

Routable Layout

Strategies to Fix Congestion

 Modify the floorplan: 

• Mark areas for low utilization.

• Top-level ports

    Changing to a different metal layer. 

    Spreading them out, re-ordering or moving to other sides .

• Macro location or orientation 

    Alignment of bus signal pins. 

    Increase of spacing between macros .

    Add blockages and halos. 

• Core aspect ratio and size 

    Making block taller to add more horizontal routing resources. 

    Increase of the block size to reduce overall congestion. 

• Power grid 

   Fixing any routed or non-preferred layer.

Placement Flow in IC Compiler Tool  From Synopsys

Placement Flow

1-Pre-Placement Checks: Ensuring design constraints are met before starting placement.

• Specificy Routing Layers minimum and maxium 

set_ignored_layers -min_routing_layer " mention_specific_metal_layer " -max_routing_layer " mention_specific_metal_layer "

• Report Routing layers 

report_ignored_layers

• Check preplacement stage make sure that you don't have errors from Message browser

check_design -checks pre_placement_stage -open_message_browser

• check constraints

check_physical_constraints

2-Insert buffers and inverts: chose clock gates for High Fanout synthesis.

• select clock gate use set_lib_cell_purpose command.

set_lib_cell_purpose -include none {get_lib_cells */CKBD* get_lib_cells */CKND* get_lib_cells */CKND2D*  get_lib_cells */CKXOR2D* get_lib_cells */CKAN2D*} 

• Confirm that the placement site called unit is set as the default site definition (should be true):

get_attribute [get_site_defs unit] is_default

• Confirm that Y-symmetry is applied to the standard cells:

get_attribute [get_site_defs unit] symmetry       

                                                        

3-Setting options: set options for placement commands Its modatariy .

• set the options

 set_app_options -name plan.place.auto_generate_blockages -value true

 set_app_options -name place.coarse.fix_hard_macros -value false

• The advanced legalizer is generally recommended for 12nm technologies and below

 set_app_options -name place.legalize.enable_advanced_legalizer -value true

• setting options for congestion_driven restructuring 

 set_app_options -name place.coarse.cong_restruct -value on

 set_app_options -name place.coarse.cong_restruct_strategy -value original

• if you don't have scandef  block  set value true else false

set_app_options -name place.coarse.continue_on_missing_scandef -value true

• setting options Timing_driven  Restructuring choices: area, area_timing, timing, timing_power.

 opt.common.advanced_logic_restructuring_mode -value timing

• Layer Optimization / Route Driven Extraction (RDE): global routing is run on the initially placed design to construct an RDE extraction table This improves the pre- to post-route timing correlation.

 set_app_options -name place_opt.flow.optimize_layers -value true

 set_app_options -name opt.common.enable_rde -value true

4-Placement Commands: create placement after setting options .

• place standard cells inside core but not legalized

 create_placement -floorplan -effort high

• legalize standard cells inside core 

 legalize_placement 

• optimize placement

 place_opt         

• enhance the placement                                                                                            

 refine_opt    

                                                                                               

 

5-reports: After placement, various reports are generated to validate the placement quality  .

• reports placement violators 

 report_placement -physical_hierarchy_violations all -wirelength all -hard_macro_overlap -hierarchical 

• check pin placement

check_design -checks pin_placement 

• report congestion

 report_congestion 

• check legalization

 check_legality -verbos 

• report setup timing

report_timing -nosplit -delay_type max 

• report hold timing

report_timing -nosplit -delay_type min 

• report violating constraint for setup

report_constraint -all_violators -nosplit -max_delay

• report violating constraint for hold

report_constraint -all_violators -nosplit -min_delay 

                                                  

                                                             

 

6-save placement state: save the placement stage .

• Use save_block command

save_block -as ${design}_placement