FloorPlanning

what's the FloorPlanning ?

Floorplanning is specifying the actual area of chip layout and placement of  physical cells(.lef).

After design setup , we need to decide the location of IPs/Macros, I/O pads, power pads , hierarchal/flat.  

what's the Target of floorplanning ?

Minimizing  area , delay and congestion for routing 

The Big Picture of VLSI design floorplanning 

After Floorplanning we have the exact area of chip and actual placement of i/o cells and macros  

• If i/o pads specify the chip size it's called pad limited design                                                                                               

pad limited

                                                                                                                               

•  If cells area specify the chip size it's called core limited design     

core Limited 

                                                                                                                                                                                                                   

 ASIC floorplanning steps

1- first define the routing direction for each metal in technology file (.tf)

  set_attribute [get_layers M1] routing_direction horizontal                                                                      

 set_attribute [get_layers M2] routing_direction vertical                                                                           

 set_attribute [get_layers M3] routing_direction horizontal                                                                        

 continue  repeating command for all metals .

2- specify chip size the core and die area  

If  I want to create the Asic chip with area of core use side_length option , core offset to specifiy die area  

• die width   1700 
• die Hight    1500
• core width 1500 
• core Hight 1300

command is 

initialize_floorplan -side_length {1500 1300} -core_offset {100 100 100 100} -flip_first_row true                

chip size 

Utilization is the percentage of core area that is taken up by standard cells 

                                          Utilization = total cell area/core area 

standard utilization is 70% but it can vary depend on your design 

If you have high utilization make it difficult to route ,high congestion .

• you can use initialize_floorplan -core_utilization ratio , Icc tool gives you the utilization percentage if you are using exact measurements as previous  

Estimate Utilization

Aspect ratio  is the ratio between width and Hight of chip

• default is 1 

GUI  flow 

Here's the chip size GUI window you can use it for more options like U ,L ,H shape ,etc

GUI of  chip size

3- create the i/o guide which i/os replaced 

create_io_guide -name {left} -side left -line {{0 110} 1335}                                                               

create_io_guide -name {top} -side top -line {{110 1445} 1335}                                                        

create_io_guide -name {right} -side right -line {{1445 1335} 1335}                                                   

create_io_guide -name {bottom} -side bottom -line {{1335 0} 1335}                                                 

4- create corners pick the name of corner cells from .lef and place it in 

create_cell {CORNER1 CORNER2 CORNER3 CORNER4} ExplorationWorkspace_physical_only:(name_of_corner).frame

5- create i/o guide for each i/o cell 's location (it's not mandatory to do)

• -io_guide_object choose which side 
• -constraint  i/o pads name 

set_signal_io_constraints -io_guide_object  side_name   -constraint {pad_1 pad_2}                                  

👉 another option for exact location with measurements use this command and the previous command 

create_io_guide -name {side _name }   -side side _name  -line {{measurements}measurements }   -pad_cells {pad_1 pad_2}  

6-place io in guide locations  you can use it without step 5 

place_io                                                 

i/o placing 

7-make boundaries for hierarchy in FloorPlanning (don't use it if you are working on flat design) 

1. From view icon choose > Logical Hierarchy 
2. Select a logical hierarchy block
3. Select Create Module Boundary from the context menu, or click the Create button in the Module Boundaries section of the Hierarchy Exploration panel

Hierarchy blocks 

explore_logic_hierarchy -create_module_boundary -cell {block_name}                                   

8- macros placement 

First: highlight macros 

set macro_cells [get_cells -physical_context -filter "is_hard_macro && !is_physical_only" -quiet]                    

second: orientation 

The orientation of macros must be in vertical ,the same orientation of ploy layer in fabrications .

set_macro_constraints -allowed_orientations {R0 R180} $macro_cells                                                        

• report the constraint for macros 

report_macro_constraints                                                                                                                             

Third: macro's keepouts

• Placement blockage

Placement blockage of macros are areas that the tools should not place any cells.

there are several types :

1. Hard Blockage – no cells can be placed inside.
2. Soft Blockage – cannot be used during placement, but may be used during optimization
3. Partial Blockage – an area with lower utilization. 
4. Halo (padding) – an area outside a macro that should be kept clear of standard cells

• Commands

Highlight macros

set all_macros [get_cells -hierarchical -filter "is_hard_macro==true"]                                                             

Hard Blockage

create_keepout_margin -type hard -tracks_per_macro_pin distance  $all_macros                                        

Hard  Macro Blockage

create_keepout_margin -type hard_macro -tracks_per_macro_pin distance $all_macros                               

Soft Blockage 

create_keepout_margin -type soft -tracks_per_macro_pin distance $all_macros                                           

• Routing blockage

 Routing Blockage is defined for a given layer

create_keepout_margin -type routing_blockage -layers "metal layers"tracks_per_macro_pin

 distance $all_macros

fourth : submit macro's keepouts constraints by two options 

set_app_options -name place.coarse.fix_hard_macros -value false place.coarse.fix_hard_macros 

 false

set_app_options -name plan.place.auto_generate_blockages -value true plan.place.auto_generate_blockages true

fifth : placment  

create_placement -floorplan -effort high                                                                                                           

• Check violation

report_placement -physical_hierarchy_violations all -wirelength all -hard_macro_overlap -hierarchical             

Sixth : Fix  macros and i/os

 use command or highlight macros and i/os from gui

set_fixed_objects $all_macros                                                                                                                       

To move standard cells out the core use 

reset_placement                                                                                                                                           

9-Save FloorPlanning stage

save_block -as ${design}_floorplanning