Synthesis to Place and Route (PnR): A Comprehensive Workflow Overview

Place and route 

Synthesis to Place and Route (PnR) Workflow

Ideal Assumptions During Synthesis

During synthesis, the following ideal assumptions are typically made to simplify the process:

• Gate-Level Netlist (.V): The netlist generated contains connected cells from the PDK but lacks details like power connections.
• No Power Connections: Power connections are not defined in the initial netlist.
• Timing Arcs: Ideal conditions are assumed, with clock skew set to zero.
• Area Estimates: The area requirements are based on estimated interconnection parasitics rather than actual routing data.

Transitioning from Logical to Physical View

When moving from the logical synthesis to the physical design:

• Remove Ideal Assumptions: Adjust the design to reflect non-ideal conditions.
• Define Power Nets: Establish power connections in the design.
• Define Modes: Set up different operational modes, such as hold and setup timing checks.. ng.

Post Place-and-Route (PnR) Validation

After completing the place-and-route phase:

• Verify Timing, Power, and Area: Ensure that the design meets the specified timing, power, and area requirements.
• Check DRC and LVS: Perform Design Rule Checking (DRC) and Layout Versus Schematic (LVS) checks to ensure the design adheres to manufacturing constraints.

PNR inputs and outputs files 

Inputs and Outputs

Inputs to Physical Design:

• Constraints (SDC files): Define timing and other constraints for the design.
• Library Files (.lib): Provide timing, power, and functional information for the standard cells.
• Gate-Level Netlist (.v): The synthesized netlist containing connected cells from the specific Technology node (PDK) .
• Parasitic Files (TLU+): Used to model the parasitic effects during routing.
• Mapping Files (.map): Map the technology layers to parasitic data.
• LEF Files (.lef): Abstracted physical view of the standard cells, including cell size, pin locations, and blockages.
• Technology Files (.tf): Contain technology-specific information like metal layer properties.

Outputs from Physical Design:

• Layout (.lef): The physical layout, which can be merged for final design.
• Verilog (.v): Updated netlist after placement and routing.
• Timing Reports (.rp): Reports generated to verify timing compliance.

PnR workflow in ICC2/ICCII compiler from Synopsys 

you have to setup the NDM library for ICC2 compiler 

Setting Up the Library

To begin working in ICC2, you need to create a library using the NDM format. Here’s how:

1. Opening the GUI:

To manage the library using command-line instructions:

open terminal in ndm empty folder and write a command to open gui  

icc2_lm_shell -gui                                                                                                         

• A window appears with three options :create a new library or edit the existing library or view an existing library  Choose "Create New Library.

2. Workspace Exploration Setup:

• Upload the technology file (.tf) from your PDK.

• Upload all relevant DB, LEF, and GDS files from the PDK and click "Read."

3. Group Libraries:

• Click on the "Group Libs" icon and then the "Process Workspace" icon.

choose Group Libs icon then  process workspace icon  

• If you encounter errors, add missing files in the "Read Source File" section. You can verify details like the number of cells and PVT corners in the Exploration Workspace

Command Flow for Library Management

To manage the library using command-line instructions:

library manager flow 

        
         # Create a new workspace for exploration
    create_workspace -flow exploration -technology /techfiles/name.tf ExplorationWorkspace

	# Read the necessary database files
	read_db { sc.db io.db macro.db }

	# Read LEF files with merge action set to Add
	read_lef -merge_action Add { sc.lef io.lef macro.lef }

	# Read GDS files with merge action set to Add and trace option set to auto
	read_gds -merge_action Add -trace_option auto { sc.gds io.gds macro.gds }

	# Change selection to the created workspace
	change_selection [get_workspaces {ExplorationWorkspace}]

	# Group the libraries
	group_libs

	# Process the workspaces
	process_workspaces

	# Re-select the workspace after processing
	change_selection [get_workspaces {ExplorationWorkspace}]     
        
    

PnR Flow: Setting Up Inputs to IC Compiler ,Reading input files

1. Specify the Design Name:

set design design_name                                                                                                

2- create_lib containing .ndm

create_lib -technology /technology file path/techfiles.tf -ref_libs (macro.ndm sc.ndm i/o.ndm physicalonlycells.ndm) $design                                                                       

3-read_paracitics tluplus file 

read_parasitic_tech -tlup /techfiles/tluplus/name.tluplus -layermap /techfiles/tluplus/name.map 

4- read verilog (output synthesis verilog )

read_verilog /output/name.syn.v -library $design -top topdesignfilename      

link_block

5- reading  constraints 

• if you are using .sdc  

read_sdc /output/name.sdc                                                                                    

• if you are using .tcl     

source /constraints.tcl                                                  

6- save the block 

save_block -as ${design}_setup