Exploring Synopsys Design Constraints (SDC) for ASIC Design : Input and output Delays, boundaries (part3)

Input and Output Delays in Static Timing Analysis (STA)

When designing digital circuits, it is crucial to define the timing characteristics of the input and output ports to ensure proper data transfer and synchronization within the design. The commands set_input_delay and set_output_delay in Synopsys Design Constraints (SDC) format are used to specify these timing characteristic

Input Delay

Clock specification for input delay

Clock Specification for Input Delay:

• -clock clock_name: Specifies the reference clock that triggers the signal reaching the input port. This is typically the clock that drives the launching flip-flop or latch.
• -clock_fall: By default, it is assumed that the delay specified is with respect to the positive edge of the clock mentioned. However, if the flop F1 is triggered by negative edge of the clockthen option -clock_fall needs to be added.
  
  
• -level_sensitive: Used when the launching device is a latch. It accounts for time borrowing by the launching latch.

Delay Type:

• -min: Qualifies the delay value as the earliest arrival time, used for hold checks.
• -max: Qualifies the delay value as the latest arrival time, used for setup checks. Without -min or -max, the specified value is used for both.
• -add_delay: Allows specification of input delays with respect to multiple reference events on the same port.

Output Delay

For output ports, the set_output_delay command specifies the timing for signals traveling outside the block before being sampled by the receiving flip-flop.

1. Clock Specification for Output Delay:

   • Reference clock for output delay is typically the clock that triggers the sampling flip-flop or latch at the receiving end.

2. Common Mistakes:

   • New designers often confuse the reference clocks for set_input_delay and set_output_delay. The launching clock should be used for set_input_delay, while the sampling clock should be used for set_output_delay.

Miniman and Maximin Delay

It is not always possible to specify the exact time at which the signal would be available at an input port. There could be multiple paths from the same reference event  or even PVT variations could cause some degree of uncertainty as to when the signal will reach the input port

Data valid window 

Data Valid Window

The designer needs to specify the earliest time at which a signal can change at the input port. This also means the minimum time before which the input signal will not reach the input port. Consequently, the previous value will be held at the input port until this time. This minimum value is useful for ensuring that the input signal does not violate the hold requirement on a flip-flop. The designer also needs to specify the maximum time within which the input signal will surely be available at the input port. This also means the latest time within which all changes to the signal will be available at the input port. This maximum time is used to ensure that the signal meets the setup requirement of the flip-flop.

Minimum time: Ensures the previous value is held until this time, useful for hold checks.

Maximum time: Ensures the signal meets setup requirements by being available within this time.

Common Mistakes for New Designers

While specifying set_input_delay, new designers often use the sampling clock as the reference clock, whereas it should be the launching clock. Conversely, while specifying set_output_delay, they use the launching clock as the reference clock, whereas it should be the sampling clock. In many designs, the sampling and launching clock might be the same, so it might not matter. However, understanding this conceptual difference becomes important if the two clocks are not the same.

Input Transition and Output Load

1. Input Transition:

   • Without specification, the transition time is assumed to be 0, which is unrealistic.
   • Transition information can be specified using:
     • set_drive: Specifies the resistance of the driver.
     • set_driving_cell: Specifies the transition using a cell from the library.
     • set_input_transition: Specifies the transition time directly.

2. Output Load:

   • Without specification, the load is assumed to be 0.
   • Load information can be specified using:
     • set_fanout_load: Specifies the fanout count number at the output port.
     • set_load: Specifies the capacitance value directly.

Wire Load Model

• The set_wire_load_model command specifies the wire load model to be used, based on the total cell area, which is crucial for accurate delay calculations.

Example Commands

        
# Example of set_input_delay
set_input_delay -clock clk1 -max 5.0 [get_ports in1]
set_input_delay -clock clk1 -min 2.0 [get_ports in1]

# Example of set_output_delay
set_output_delay -clock clk2 -max 6.0 [get_ports out1]
set_output_delay -clock clk2 -min 3.0 [get_ports out1]

# Example of setting input transition
set_drive 1 [get_ports in1]
set_driving_cell -lib_cell AND2X1 [get_ports in1]
set_input_transition 0.5 [get_ports in1]

# Example of setting output load
set_fanout_load 4 [get_ports out1]
set_load 0.1 [get_ports out1]

# Example of setting wire load model
set_wire_load_model -name "wlm1"    
        
    

These commands ensure the correct timing constraints for both input and output ports, providing a reliable framework for timing analysis and optimization in digital circuit design.