Exploring Synopsys Design Constraints (SDC) for ASIC Design : Clock Paths and Generated Clocks (part1)

 

After reading your HDLS , you have to source your constraint file.TCL  ,The constraint file typically refers to an SDC file (Synopsys Design Constraints). This text file plays a crucial role in ensuring the correct behavior and performance of your design by specifying various timing constraints.

DC Flow

what you can find inside an SDC file for ASICs ?

To answer this is question we are going to divide the constraint file into sections :

• First section for clock paths

1-main clock and frequency:

A path which feeds into the clock pin of a flop is called the clock path . So clock path could be from the clock port till the flop ’s clock terminal, from the output of a clock divider or clock generator circuitry till a flop ’s clock terminal, etc. We have used the word “flop ” to mean any synchronous element, e.g., memory.

The SDC command is create_clock
create_clock options 

•  -period  option is used to specify the period of the clock. The unit of clock period is inferred from logic library (.lib).Identifying the Clock Source These source objects can be port, pin, or net When defining a clock on a net, ensure that net has a driver (either a pin or a port). Otherwise the clock will not have a source.For example the command will be create_clock -period 10 [get_ports clk],create_clock -period 10 [get_nets clock_Net] 

•  -name option to specify a name of clock maybe the tool choose name by own. Once a clock has been defined and given a name, all other SDC commands that depend on a clock would just refer to the name, rather than providing any other characteristics.

•  -waveform option specified the duty cycle of a clock is . This option is typically an ordered pair of real numbers, representing the rising and falling edge of a clock. The numbers indicate the time when the rise and fall edge happen after time.   

• -comment  option takes a string as its argument and is mainly used to document information about the clock to facilitate understanding, reuse, and portability of SDC and has no impact on synthesis or timing. For example create_clock -period 10 -name clk [get_ports clk]  -comment “main Clock ”

2- Generated clock

Nowadays we are  working at different speeds are usually triggered by different clocks. Each portion operating on its own clock could bring in asynchronicity in the design. This may result in several clocks being derived from one master clock. Such clocks are referred to as generated clocks or derived clocks . These clocks can be generated in multiple ways: 

• Clock dividers generate a clock of higher period and lower frequency compared to the original source clock. For example  a clock divider is a 2-bit ripple counter LSB divide by 2 and MSB divide by 4

 2-bit ripple counter

• Clock multipliers is a circuit where frequency is increased and clock period is decreased for faster clocking rate. This technique is typically used in microprocessors and on internal busses so as to improve the overall throughput of the processor .For example use buffer and invertors.

A simple clock multiplier 

• Clock gating  technique has become very popular since mid-1990s to reduce power consumption. Power in a circuit is consumed when a flop or register in the design switches state due to a clock trigger. However in a design portions of the logic may not be getting used at certain times. During that stage, disabling clock to those portions of the design reduces the switching power. This is achieved by having enable.

            Gated clock

The SDC command is create_generated_clock

create_generated_clock options 

•  -source (clock_source_pin) :This indicates the master clock source pin from which the generated clock is derived. 

•  -master_clock (master_clock_name) :This option takes the name of the SDC clock that has been defi- ned to drive the master clock source pin. Once a generated clock has been defined, the clock characteristics (waveform , period , etc.) would be derived by the tool, based on the characteristics of the waveform at the source.

•  -name  (generated_clock_name) Like the primary clock, a generated clock is also identified by its name. This is specified as string using the -name option. When -name is not specified, tools might assign a name on their own

•  -edges (edge_list) The count of edge create_generated_clock  starts with “1” and this number (“1”) represents the first rising edge of the source and (“2”) for first falling of source pin ,etc   can be used instead of  divide_by or  multiply_by  .

•  -divide_by this represents a generated clock where the frequency has been divided by a factor, which means the period is multiplied by the same factor. 

•  -multiply_by  this represents a generated clock where the frequency has been multiplied by a factor, which means the period is divided by the same factor. 

•  -invert the generated clock is defined (inverting or non-inverting) must be with  multiply_by and  divide_by.

Divide-by-two circuit with a non-inverting clock

Divide-by-two circuit with an inverting clock

•   -duty_cycle percent to determine duty cycle. This option has meaning only with multiply_by option and represents the percentage of the pulse width when the multiplied clock is 1

•  -combinational In a source-synchronous interface, clock appears along with the data as an output. The advantage of this mechanism is that both clock and data are routed through similar traces and thus have very similar delays. At the receiver device, the incoming data is sampled with respect to the incoming clock Like CLKOUT .

Source-synchronous interface

•   -add there can be more than one clock defined at a point. Or, for a given source, multiple clocks could be reaching the source

Block driven by off-chip multiplexer with two clocks

•  -comment comment_string same as primary clock