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Understanding Semiconductor Process Design Kits (PDKs): Essential Components and Acquisition

chipworld


 What is the PDK ?

A process design kit (PDK) is a set of files used within the semiconductor industry to model a fabrication process for the design tools used to design an integrated circuit. The PDK is created by the foundry defining a certain technology variation for their processes. It is then passed to their customers to use in the design process.

Getting a PDK

The only way to get an industrial PDK is to ask the fab for it. If you are a student, here is an example of an open-source PDK:
What is inside industrial  PDK ?

          You will receive:
  • Documentation files, one for I/O and one for standard cells, maybe more. It is important to take your time reading them carefully because they have a lot of rules you will use later.
  • Frontend and backend files for standard cells.
  • Frontend and backend files for I/O cells.
  • Backend files for bond pads, which don't have a logical view.
  • DRC (Design Rule Check), LVS (Layout vs Schematic), PEX (Parasitic Extraction) rules, etc.

Some PDKs that come from the fab have separate files, one for the frontend and one for the backend. You have to check you received all the files you need using the RELEASE NOTE (rln.pdf). The release note includes information for standard cells, I/O cells, and bond pad cells.

RELEASE NOTE (rln.pdf) also contains:

  • Library information like library name, version, type (standard cells or I/O cells), technology node, and which design rule file you will use.
  • Update history for this library.
  • Table of PVT corners.
  • Known problems such as rules violations that can be waived.
  • A table of library content.
  • Notes on using these cells.
  • Required tapeout layers.

As discussed, we have frontend and backend files for standard cells, I/O cells, and bond pad cells.

What is the frontend files ?

  • vlg: Verilog model, one with power and one without power, for simulation purposes after synthesis or layout Verilog netlist. It represents each technology cell.
  • vit: Vital (VHDL) model, similar to vlg, but for VHDL language. Used for simulation purposes after synthesis or layout VHDL netlist.
  • nldm: Non-linear delay model (logic view) (.lib, .db).
  • doc: Documentation for each logic cell (.lib) for each corner. For example, if you have a .lib called ss0p95v125c, you must have a .doc with the same corner.
What is the backend files ?
  • apf: Apollo/Astro FRAM (phantom) view (.lef) used for ICC compiler tool and Astro from Synopsys.
  • apt: Apollo/Astro FRAM and CELL (layout) view, similar to apf but with more details.
  • sef: Silicon Ensemble/SOC Encounter LEF (phantom) view, similar to apf (.lef), used with specific EDA tools like ICC2 compiler from Synopsys and SOC Encounter tool from Cadence.
  • lpe: Layout parasitic extracted SPICE netlist for LVS extraction flow.
  • gds: GDSII layout view, considered the cell view of cells needed for physical verification flow, with more layout details than apf.
  • spi: SPICE/LVS netlist needed for LVS flow and SPICE simulation.
Extra files in process design kit (PDK)

  • mdt: Mentor DFT
  • ctc: CeltIC CDB 
  • ibs: IBIS model 
  • cdk: Cadence design kit 
  • vcn: Magma Volcano database
Key Tips
  • you must check you have all these views before you start .
  • If you got only frontend files , ask the fab for backend files incase if you have a separate PDk files ,because sometimes it takes long time ( at least 4 months).

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