Logic Synthesis with Synopsys Design Compiler (DC) : A Step-by-Step Tutorial - part 1

Logic synthesis is a critical step in the digital design process, converting behavioral RTL (Register-Transfer Level) descriptions into a gate-level netlist specific to a particular technology node. This transformation is essential in bridging the gap between abstract design specifications and the actual hardware implementation.

What is the logic synthesis ?

Synthesis is the process of transforming RTL code, which describes the functionality of a digital circuit, into a gate-level netlist. This netlist is composed of basic logic gates and flip-flops, optimized for a specific technology node. 

The use of logic synthesis can effectively translate this is designs and optimize for area ,speed ,power .

Counter example

Inputs to this stage :

• synthesized RTL:The behavioral description of the design in a language like Verilog (.V) or VHDL.
• logic library : Files such as (.lib) or (.db) that describe the characteristics of the technology-specific standard cells used during synthesis..
  
• constraint file: Typically a (.tcl )file that specifies design constraints like timing requirements.

outputs from this stage :

• gate level netlist :The final netlist that maps the RTL description to specific technology nodes' gates. 
• constraint (SDC) :Synopsys Design Constraints file for post-synthesis optimization.
• reports: Detailed reports on area, timing, and power. .
• standard delay format (.sdf): A file used for timing simulation and verification.

Synthesis Flowchart  

Synthesis Flow

Synthesis Tools: DC Compiler vs. RTL Compiler

Both DC Compiler (from Synopsys) and RTL Compiler (from Cadence) are popular EDA tools for synthesizing RTL code into gate-level netlists. However, they have some key differences:

Feature	DC Compiler	RTL Compiler
Target Audience	General-purpose synthesis	Emerging tool
Strengths	Extensive technology library and optimization options	Fast synthesis engine
Weaknesses	Limited support for advanced features	Relatively new tool
Synthesis Engine	Classic two-pass engine	Modern multi-pass engine
Memory Management	Heap-based memory management	Stack-based memory management
Constraints	Extensive support for SDC constraints	Limited support for SDC constraints
Scripting Interface	Tcl scripting language	Python scripting language
Cost	More expensive	Less expensive
Availability	Available on multiple platforms	Primarily available on Windows

Using DC Compiler for Synthesis Flow

DC Compiler is widely used in the industry due to its robust features and extensive library support. Here's a basic flow for using DC Compiler:

Design compiler Flow

DC starts with Develop your RTL ,Here's some rule to prepare your RTL to pass synthesis. 

Modified RTL

What's the Non synthesizable statements in verilog?

 In your RTL code you have to check  Non synthesizable statements.

Develop Your RTL

• Ensure your RTL code is ready for synthesis by removing non-synthesizable statements.
• Non-synthesizable statements in Verilog include delays (# time), primitives, tasks, ===, !==, initial block, release, and force.

Instantiate I/O Cells:

• If working on a die (not just the core), instantiate the I/O cells and connect the logic pins.Example: Dual-Driving Regular I/O Cell with Schmitt Trigger Input and Enable-Controlled Pull-Down Resistor you need to instantiate the io cells and connect the logic pin if you are working on die not core only

input & output pad

Here's the truth table for how to configure the programmable pins

The OEN (output enable) control pin I→ PAD

The IE (Input enable) control pin PAD→ C

Here’s an example of how to instantiate and connect the I/O cell as an input, along with the necessary connections for control pins using tiehigh and tielow cells:

        
wire logic0;   
wire logic1;

// Instantiate the tiehigh and tielow cells to generate logic levels
TIEH tie_H (
    .Z(logic1)  // Connects to logic 1
);

TIEL tie_L (
    .ZN(logic0) // Connects to logic 0
);

// Instantiate the I/O pad and configure it as an input
iopad_instance PAD_name (
 .PAD(Input_name),// External input pad
 .C(pin_to_core_name),// Connects to the core logic
 .IE(logic1),// Input enable tied to logic 1 (enabled)
 .OEN(logic1),// Output enable tied to logic 1 (disabled)
 .I(logic0),// Input to pad tied to logic 0 (unused it's configured as input)
 .DS(logic0),// Drive strength tied to logic 0 (unused in input configuration)
 .PE(logic0) // Pull enable tied to logic 0 (no pull-up or pull-down)
);

// Instantiate the macro or IP block
macro_circuit macro_name (
    .inputs(),  // Connect your specific inputs here
    .output()   // Connect your specific outputs here
);    
        
    

Explanation:

1. Tiehigh and Tielow Instantiation:

   • TIEH generates a logic high (1) signal, connected to the wire logic1.
   • TIEL generates a logic low (0) signal, connected to the wire logic0.

2. I/O Pad Configuration:

   • The I/O pad instance (iopad_instance) is configured as an input.
   • The control signals IE (Input Enable) and OEN (Output Enable) are both tied to logic 1 using tie_H, which enables the input functionality and disables the output.
   • Other signals (I, DS, PE) are tied to logic 0 using tie_L, as they are not needed for an input configuration.

3. Macro or IP Block Instantiation:

   • Finally, instantiate the macro or IP block and connect its inputs and outputs according to your design specifications and datasheet.