Understanding Key Files in Physical Design

what's the ( .lef ) file ?

As we discussed (.lib) logical view , we have (.lef ) physical view of cell ,it's a readable ASCII format that contains detailed PIN information that is used by PNR tools .

The LEF  file abstract the following information to PNR tools:

• Cell size and shape.
• Pin locations and Layer.
• Metal blockages area (OBS section).

what's the difference between .lef and .gds view?

• .lef (FRAM view) mainly  it's abstracted view, it doesn't have all details, For Example  if you open in icc2 compiler for a specific cell you notice that not all metals appear in compiler .
• .gds (Cell view ) it has all details for you cell ,all metals .

We are using .lef view during place and route cause it fast, and merge all .lef with .gds at the end of layout design for physical verification DRC and LVS check.

I 'll give you an example of corner cell library (physical only cell) in .LEF and .GDS to show you the difference between them .

corner cell .gds

corner cell .lef

you can see that the .GDS format has more details. in IC2 compiler we use .lef .but  in IC compiler we use something similar to .lef and .GDS called milkyway library.

what is the Milkyway  Database ?

The milkway library contains physical information about standard cells , macros/IPs cell , I/O cells and other physical only cells like corner ,fillers, etc. The milkway database was originally developed by Avanti corporation which has since been acquired by Synopsys in 1997 .

Milkway is the database underlying most of Synopsys 's physical design tools.

 milkyway database contains layout and abstract views :

1. layout (CEL view ) contains drawn mask layers required for fabrication.

2. Abstract (FRAM view) contains only minimal data needed for PnR tools [ pin shapes ,obstructions].

FRAM and CEL view in nangatepdk

The difference between both views is like the difference between .GDS and .LEF views

The IC compiler tool from synopsys uses milkway reference to obtain physical library information .

what is the Technology file (.tf) ?

The technology file provides technology specific information ,such as the metal layer color ,number ,default width, min width, min spacing. This seemingly cryptic document holds the key to understanding the rules and regulations that govern the placement and routing of cells on a chip. But fear not! We'll explain what each section of a .tf file means, using the example of FreePDK45_10m.tf from Nangate.

section of technology file

• Layers:

This section is the foundation of chip design, defining the different metal layers used for wiring (M1, M2, etc.). Each layer has its own color code (in RGB format) and design rules specifying minimum width and spacing for proper functionality. Additionally, antenna data ensures optimal signal integrity, and preferred routing directions optimize placement for efficient connections.

example of metal layer 4

for each metal layer has text layer with same number , if you are working on 6 metal layers , so you have 6 text layers , used for labels in your layout.

example of text layer 4

• Sites:

Think of sites as the building blocks of your chip. This section defines the grid system for placing standard cells, with core sites representing the minimum cell size. Special site definitions cater to the unique needs of input/output (IO) cells.

• Vias:

These tiny structures act as bridges between different metal layers, ensuring seamless signal flow. Via definitions specify their size and location, enabling proper connections without violating any design rules.

example of Via

• Units:

Accuracy is paramount in chip design. This section defines the default units used for various parameters like time, power, and resistance, ensuring consistency and clarity throughout the file.

Layout compiler calculates interconnect C and R values using net geometry and the TLU+ look-up tables.In some of PDK provide only an ITF(Interconnect Technology Format) single process file., that you use this file to generate tluplus files

What's the TLU-plus ?

The TLU-plus files define models for calculating ultra-deep-submicron RC parasitic values from extracted wire data. These files and libraries are provided in PDk or a library group.

If the vendor did not provide TLU+ files, the user can generate TLU+ from ITF data. This requires a Star-RCXT license:

generate TLUPLUS files

 unix% grdgenxo -itf2TLUPlus -i <ITF file>  -o <TLUPLUS file>                                                         

 where: -itf2TLUPlus generates TLUPLUS files

 -i is the ITF file

 -o is the output, binary TLU+ model file 

ITF file for Cmax 10 metal layers

When generating TLUPlus models with grdgenxo, the –itf2TLUPlus option must be the first option specified. Always use the latest Star-RCXT release to generate the models. More and more ASIC vendors are supporting TLU+ models and they may provide the binary cap table files for your use. If possible, generate TLU+ models for at least two operating corners Cmin from ITF Cmin and Cmax from ITF Cmax, ITF file is readable but TLU+ not readable file.

What's the Mapping file (.map)?

The Mapping File maps the technology file (.tf) layer/via names to Star-RCXT (.itf) /TLUPLUS files layer/via names.

Mapping file .map